Draw a digit. A 161 x 111 µm chip classifies it.

This is a weight stationary INT4 dot product accelerator that fits one Tiny Tapeout tile on SkyWater sky130. It does 2 multiply accumulates per clock. The page runs the chip's exact integer arithmetic in your browser: 4 bit weights, 4 bit pixels, a 20 bit saturated sum. An AI agent pipeline designed and verified it. It has not been fabricated.

2.0INT4 MAC per clock
+9.43 nsslack at 50 MHz, slow corner
0 / 0DRC / LVS errors
3,600dot products bit identical on RTL

Input

What the chip sees: 8 x 8 pixels, each 0 to 7 (4 bit). Two pixels per byte, 32 bytes per image.

Chip output

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Draw a digit 0 to 9, large and centered.

Bytes on ui_in[7:0]

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Low nibble first. The host loads each class's 64 weights in chunks (LOAD pin), then streams pixel bytes at one byte per clock. Each byte carries two products, so one clock retires 2 MACs. Bias and argmax run on the host.

The layout

GDS render of the sky130 layout

Open the 3D layout viewer · 76.9% placement utilization · about 1.05 mW at 50 MHz (estimate)

What is measured and what is not

Measured: for the 360 test images, every one of the 3,600 dot products the RTL produced matched Python bit for bit (95.56% accuracy, 115,760 chip clocks for the whole batch). The layout passed the official Tiny Tapeout flow with DRC 0, LVS 0, antenna 0, and the post layout gate netlist passed 6 of 6 stress tests. Random test image shows those verified dot products.

Modeled: a digit you draw is classified by a JavaScript copy of the same integer math, not a simulation of the netlist. Not measured: silicon, and the RP2040 PIO host on a real demo board (co simulated at about 16 MHz chip clock).