Custom chips on Tiny Tapeout · sky130
You write a cycle-level Python model of what the chip should do. An AI agent writes the Verilog. You only get it back after it matches your model bit for bit, catches injected faults, and passes the official Tiny Tapeout layout flow.
Pilot: the first 10 orders are free. Next shuttle closes 2026-11-30.
A chip that matches a vague spec is a guess. A chip that matches your Python model on every clock is not. Write the model here, run it on random inputs, and look at the waveform before you order. This runs the same loop as the cocotb test that ships in your repo, in your browser, nothing uploaded.
The contract: Model.reset(), and Model.cycle(ui_in, uio_in) returns (uo_out, uio_out, uio_oe) as seen just before the next rising edge, then advances one clock. Optional stimulus(rng, cycles) yields (ui_in, uio_in[, rst_n]) so the test drives your protocol, not noise.
The agent only writes Verilog. Your model and the test are fixed, and it cannot touch them. Every failure goes back to the agent with the first mismatching clock, the inputs, what your model expected and what the chip did.
Plain English for the pins and protocol, Python for the exact behaviour, including latency. Ambiguity gets settled here, not in silicon.
Catches a model that breaks its own contract before any Verilog exists.
Verilog-2005 for one tt_um_* module with the Tiny Tapeout pins. Lint errors, mismatches and size problems go back to it, up to a fixed number of attempts.
Catches lint errors, latches, wrong widths via Verilator -Wall.
The cocotb test that ships in your repo drives your stimulus every clock and compares every output pin with your model, over three seeds with a reset in the middle.
Catches off by one clock, wrong reset, X on outputs.
Yosys synthesizes the RTL and the netlist runs the same test. Then sky130 area and 50 MHz timing are predicted with a model fitted to 11 real layouts.
Catches simulation and synthesis disagreeing, designs too big for the tile.
Copies of the RTL with one operator flipped run through the test. Each one should fail. Survivors are listed in your report: either harmless or a gap in your stimulus.
Catches a test that passes anything.
Your repo runs the Tiny Tapeout gds, precheck and gate level workflows in GitHub Actions: placement, routing, DRC, LVS, antenna, timing at slow corner.
Catches anything that would get a shuttle submission rejected.
Each delivery is a public repository you can clone, re-run and submit. The badges are live GitHub Actions results, not screenshots.
Four 8 bit PWM outputs on a shared counter, duty registers loaded over the bidirectional pins.
| Cycles matched | 8,997 RTL · 8,997 gates |
| Mutants caught | 5 / 5 |
| Layout | 1x1 · 20.8% · DRC 0 · LVS 0 |
| Setup slack, slow corner | +11.33 ns at 50 MHz |
Rotary encoder input through a two flop synchronizer, 8 bit position count, sticky error on illegal jumps. The latency is part of the contract.
| Agent attempts | 1 (53 s, spec to verdict) |
Orders are GitHub issues, so the spec, the model, every agent attempt and the final report stay public and linkable. Need it private? Say so in the issue and we will move to a private repository.
First 10 orders. You pay Tiny Tapeout directly only if you fabricate.
Not sure it fits? Open the order anyway. A failed order costs you nothing and the report says exactly where it stopped.
It is a design that passes the same layout and checks Tiny Tapeout requires for a shuttle. It becomes silicon when you submit the repository and buy a tile at app.tinytapeout.com. None of the example designs has been fabricated yet, and we say so in every report.
Because English leaves the timing open. "Outputs the count" does not say which clock. A cycle-level model does, and it turns into a test the agent cannot argue with.
You get the report anyway: each attempt, the stage it failed at, and the first mismatching clock. Often that points at the model, not the RTL.
Claude, run as a tool-less code generator. It only produces Verilog text. Simulation, synthesis, mutation testing and layout are done by Icarus, Verilator, Yosys, OpenSTA and the Tiny Tapeout LibreLane flow.
Yes. Attach it to the order and it goes through the same checks without the agent. That alone is a useful second opinion before a shuttle deadline.
Kai Kim (@KaiKimLabs). The same flow designed an 8 MAC per clock accelerator and a digit classifier in one tile. Write up: kaikimlabs.com.